Flux Computing designs and manufactures optical processors to train and run inference on large AI models. Join us to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed.

The Role

We’re seeking a Senior / Staff ASIC Packaging Engineer to lead the design, integration, and optimization of advanced multi-die packages for our next-generation ultra‑high‑speed analog and mixed-signal ICs. These packages include high-speed DACs/ADCs, TIAs, sub‑100 fs‑rms jitter PLLs, and large clock-distribution networks — often in conjunction with optics die and photonic components.

You will be responsible for the physical implementation and signal integrity of complex packages, including flip-chip, 2.5D/3D ICs, and interposers, working closely with analog layout, circuit design, and optical integration teams to deliver robust, high‑performance solutions that scale.

Responsibilities

• Own the physical design and integration of multi-die packages, including optical, analog, digital, and photonic die, using flip-chip, interposer-based, or fan-out architectures.

• Develop detailed floorplans and escape routing strategies for high-density micro-bump, TSV, and redistribution layers, ensuring compliance with signal integrity, power integrity, and thermal performance targets.

• Collaborate with analog layout engineers to co-optimize chip/package interfaces, including modeling and minimizing parasitics for > 10 GHz signal paths and low-jitter clock domains.

• Perform and iterate based on EM/IR, thermal, SI/PI, and mechanical stress simulations, using tools such as HFSS, SIwave, Ansys RedHawk, or equivalent.

• Work with circuit designers and optical system architects to ensure photonic alignment, thermal stability, and coupling efficiency in packages that integrate optical dies (e.g., silicon photonics).

• Drive package substrate and interposer design in collaboration with foundries and substrate vendors, ensuring manufacturability and reliability.

• Support prototype bring-up and characterization, correlating simulation and measurement results to improve model accuracy and performance.

• Develop and maintain design guidelines, checklists, and automation scripts to streamline packaging workflows; mentor junior engineers on best practices.

• Partner cross-functionally with IC design, test, signal integrity, manufacturing, and operations teams across multiple product lifecycles.

Skills & Experience

• 7+ years of experience in ASIC/SoC packaging with a strong focus on multi-die integration, including 2.5D/3D ICs, chiplets, and optical components.

• Proven track record in designing and shipping high-speed analog/RF and mixed-signal IC packages operating at 10 GHz and above.

• Deep understanding of package parasitics, high-density micro-bump routing, return-loss/skew tuning, low-inductance power delivery, and thermal mitigation techniques.

• Experience with optical packaging, including co-packaged optics (CPO), silicon photonics integration, or VCSEL/photo-detector alignment and coupling.

• Expertise in signal and power integrity simulation tools, and package design tools (Cadence APD/SIP, ANSYS, HFSS, or equivalent).

• Familiarity with foundry and OSAT processes, design-for-manufacturability (DFM), reliability standards, and production ramp.

• Strong cross-functional communication skills; able to bridge circuit, layout, optics, and packaging disciplines in a fast-paced development environment.

Frequent travel is expected between our Austin and London offices.

We do not accept unsolicited CVs from recruitment agencies, will not be liable for any fees, and prohibit unauthorised use of our company name in recruitment activities.

We’re building fast and that includes our benefits. More exciting additions are coming soon for the Flux crew.

If you are passionate about pushing the boundaries of what's possible in AI and thrive in a high-energy, fast-paced environment, we want to hear from you. Apply now to join Flux and be a key player in shaping the future of computing.