Flux Computing designs and manufactures optical processors to train and run inference on large AI models. Join us to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed.

The Role

We are seeking a Senior Physical Layout Engineer to own the full‑custom layout of ultra‑high‑speed analog blocks that lie at the heart of the OTPU including: high speed DAC/ADC/TIAS, sub‑100 fs‑rms jitter PLLs and large multi-lane clock‑distribution meshes.

You will translate transistor‑level intent into silicon‑accurate geometry, balancing dense floorplans with the exacting parasitic, symmetry and matching constraints that high‑frequency analog demands.

Responsibilities

• Plan, execute and sign‑off full‑custom layouts for high‑speed analog/RF IP (TIAs, PLLs, CDRs, drivers, samplers, bias networks, ESD clamps).

• Drive floorplanning and top‑level integration, coordinating power‑grid, clock‑mesh and micro‑bump/flip‑chip escape routing so 100 + channels meet skew and return‑loss targets.

• Perform parasitic extraction and EM/IR, thermal and electro‑migration analysis (Cadence Quantus / Calibre xRC, Voltus, EMX / HFSS), iterate with circuit designers to close speed, noise and phase‑noise margins.

• Optimise critical paths for minimal capacitance and series inductance: shielded differential pairs, common‑centroid devices, guard rings, stitching vias and low‑impedance return paths.

• Ensure all blocks pass sign‑off: DRC, LVS, ERC, ESD, latch‑up, DFM and foundry‑specific reliability checks.

• Collaborate with packaging and signal‑integrity teams to co‑design interposer, substrate and PCB break‑outs; model bond‑wire / micro‑bump parasitics in the extraction flow.

• Create and maintain layout guidelines, checklists and Skill/Tcl/Python automation scripts; mentor junior layout engineers and review their work.

Skills & Experience

• 7 + years of custom analog/RF IC layout in production CMOS technologies, with multiple tape‑outs that include > 10 GHz analog front‑ends or 56 ‑ 112 Gb/s SerDes / CDR / PLL blocks.

• Expert user of Cadence Virtuoso custom layout tools plus sign‑off flows (PVS/Calibre DRC‑LVS, Quantus/StarRC, Voltus/RedHawk).

• Deep understanding of parasitic‑aware matching, device symmetry, shielding, differential routing, guard‑ring strategy, ESD and on‑chip power‑grid design.

• Demonstrated ability to close sub‑pF capacitance budgets and < 5 mΩ series resistance on critical nets through careful geometry selection and EM‑aware verification.

• Experience with flip‑chip, micro‑bump, 2.5D/3D IC or chiplet integration and the associated inductance / crosstalk challenges.

• Proficient in Skill, Tcl or Python to automate repetitive layout and sign‑off tasks.

• Excellent communication and collaboration skills; comfortable working across circuit design, packaging, signal‑integrity and manufacturing teams in a fast‑moving environment.

Frequent travel is expected between our Austin and London offices.

We’re building fast and that includes our benefits. More exciting additions are coming soon for the Flux crew.

If you are passionate about pushing the boundaries of what's possible in AI and thrive in a high-energy, fast-paced environment, we want to hear from you. Apply now to join Flux and be a key player in shaping the future of computing.